The numerically controlled oscillator (NCO) is a well understood and widely used circuit for generation of an output clock signal on a precise frequency from some higher frequency input clock signal. The typical circuit for a NCO consists of an N-bit adder circuit connected between a pair of N-bit registers (an input register and an output register) so as to form a continuously integrating structure. The most significant bit of the output register, which toggles once every time the integrator overflows it N-bit numerical range, can be used as a clock in some other subsequent circuit. The output frequency is given by F.sub.OUT =F.sub.W XF.sub.S, where F.sub.OUT is the frequency of the output clock, F.sub.W is an integer N-bit frequency word (less than 2.sup.N-1), and F.sub.S is the frequency step size. The frequency step size is equal to a reference clock frequency divided by 2.sup.n, where n is the number of bits in the integration path.
One requirement of a NCO is that the adder circuit must complete its summation within one clock period of the input reference clock (i.e., within a time equal to the reciprocal of the reference clock frequency). The propagation time to accomplish the summation is generally proportional to N, the number of bits used in the adder. In addition, it is well known that for a circuit structure to be implemented using complementary metal oxide semiconductors (CMOS), the power dissipation of the resulting circuit is proportional to the input reference frequency. Consequently, for applications requiring high clock speeds relative to the time required for a circuit to sum N-bits, the NCO circuit can consume considerable power. When the propagation time required to sum the N-bits is greater than a time equal to the reciprocal of the reference clock frequency, higher levels of pipelining or faster carry-look-ahead circuits are required, necessitating additional circuit elements and increasing power consumption.
The specific problem encountered was to extend a Global Positioning Satellite (GPS) chip set technology to P-code applications necessitating a receiver generating a precise P-code rate clock at a frequency of 10.23 megahertz (MHz) from a system reference clock of 38.192 MHz. In addition, the output clock was to be controllable in frequency plus or minus 30 kilohertz (kHz) around the 10.23 MHz center frequency and controllable to a resolution, or step size, of less than 0.02 hertz (Hz).
While a standard NCO circuit could be used to generate the required code rate clock, the number of bits required to achieve the desired step size would have been at least 31 bits. The adder circuit would have to complete its summation once every clock period, i.e., about every 26 nanoseconds. However, the requirement of a 26 nanosecond add time across 31 bits exceeds the limit of current CMOS switching speeds for a simple ripple carry adder structure, and cannot be designed in CMOS without the additional complexity of carry-look-ahead structures and heavy pipelining. In addition, the power dissipation from the current in the CMOS implementation would be high because the entire circuit would operate at the 38.192 MHz system clock. Additional circuit elements to decrease the addition time and spread the addition across several clock periods would necessitate even more power dissipation.
An additional alternative method to address the present problem might be to mix two frequencies with a single sideband (SSB) mixer in an exclusive-OR implementation. One frequency could be created with a slow speed NCO or incremental phase shifter, and a second frequency created by an integer divide of the system clock. While such a scheme produces the correct output frequency, the output clock would be inappropriate for use in a spread spectrum system due to the large phase error that builds up. A large amount of phase error wobble causes correlation loss in a spread spectrum system.
Thus, what is needed is an apparatus and method for low power clock generation for high speed applications which greatly reduces power consumption and eases circuit speed problems of a conventional NCO, while being suitable for use in a spread spectrum system. It is desirable that the desired range of output frequency be small and that the ratio of input to output frequency be near some ratio of integers.